9. Error Protection and Handling

9.4 Cache Error Exception

The following four internal units detect and report uncorrectable errors:

• instruction cache
• data cache
• secondary cache
• System interface

A Cache Error exception is imprecise; that is, it is not associated with a particular instruction. When any of the four units post a Cache Error exception, completed instructions are graduated before the Cache Error exception is taken. If there are Cache Error exceptions posted from more than one of the units, the exceptions are prioritized in the following order:

1. instruction cache

2. data cache

3. secondary cache

4. System interface.

The corresponding local CacheErr register is transferred to the CP0 CacheErr register and the CP0 Status register ERL bit is asserted. Instruction fetching begins from 0xa0000100 or 0xbfc00300, depending on the CP0 Status register BEV bit. The CP0 ErrorEPC register is loaded with the virtual address of the next instruction that has not been graduated, so that execution can resume after the Cache Error exception handler completes.

When ERL=1, the user address region becomes a 2-Gbyte uncached space mapped directly to the physical addresses. This allows the Cache Error handler to save registers directly to memory without having to use a register to construct the address.

The processor does not support nested Cache Error exception handling. While the CP0 Status register ERL bit is asserted, any subsequent Cache Error exceptions are ignored. However, the detection of additional uncorrectable errors is not inhibited, and additional Cache Error exceptions may be posted.*1